1. Field of the Invention
The invention relates to a method for managing a memory and more particularly, to a method for managing an external memory of a microprocessor.
2. Description of the Prior Art
Intel Corporation generally refers to a microprocessor as an MCS (Micro Computer System) and the MCS-31/32/51/52 series microprocessor developed by the Intel Corporation is commonly used in industry. Generally speaking, the MCS-31/32/51/52 series devices are 8-bit microprocessors equipped with memory and I/O ports. Take the MCS-51 microprocessor for example; it has a program memory of 4K bytes, a data memory of 128 bytes, and 32 I/O ports. Similarly the MCS-52 series microprocessor has a program memory of 8K bytes, a data memory of 256 bytes, and also 32 I/O ports. The program memory is a read-only memory (ROM) for storing programs written by a user, whereas the data memory is a random-access memory for storing data accessed by the microprocessor while it is executing the programs. The capacity of the program memory and data memory of the MCS-31/32/51/52 series microprocessors can both be externally expanded to 64K bytes, if external memory devices are employed.
For an MCS microprocessor user, an external memory with capacity of 64K bytes will not be large enough if his software has more than 64K bytes of program or data. To solve this problem, the capacity of the external memory of the microprocessor can be substantially expanded by switching a plurality of memory banks, or pages, when the user uses the extra pins of the microprocessor as decode lines to set an address for an external memory with capacity of over 64K bytes. If the external memory is one memory device with large capacity, the extra pins of the microprocessor can be address lines. If there are several external memory devices with smaller capacity, the extra pins of the microprocessor can be used to select the memory chips. Because the largest capacity of the external memory of the MCS microprocessor is 64K bytes, 64k bytes can be taken as a unit (a page) when the microprocessor switches the memory banks. As a result, the microprocessor is able to access several pages of external memory in which the programmer can store segments of his program codes. However only one page of memory is visible to the microcontroller at any moment, so the software program needs to set the state of the bank-selecting pins properly before a different page of memory can be accessed.
Further, an interrupt vector table of the MCS microprocessor is stored at a specific address of the external memory. The interrupt vector table usually comprises interrupt vectors that direct the program execution flow to the interrupt service routines. When an interrupt occurs, the microprocessor immediately fetches instructions of the corresponding interrupt vector at the specific address in the current page. Because the microprocessor does not switch memory banks when an interrupt occurs, an error will come up if the microprocessor cannot find the interrupt vector table in the current page. To solve this problem, a common area in each memory bank can be reserved for storing the interrupt vector table. The content of the common area is made identical for all memory banks, thus the microprocessor can find the interrupt vector table in whatever page the interrupt occurs. Furthermore, besides the interrupt vector table, interrupt service routines, general functions, and data for correctly switching memory banks are usually stored in the common area as well, so that they are accessible in all memory pages. For simplicity of explanation, all the program codes and data stored in the common area will be referred to as “common data” hereafter in this document.
FIG. 1 is a diagram showing the interconnections between an MCS-51/52/31/32 microprocessor and an external memory 12 according to the prior art. The capacity of the external memory 12 of the MCS-51/52 series microprocessor is expanded to 512K bytes by switching the eight 64K-byte memory banks. The external memory 12 has 18 address lines labeled A18-A0, of which A18 is the most-significant bit (MSB) and A0 is the least-significant bit (LSB). The eight LSBs (A7-0) of the memory 12 are driven by the latch 5, which holds the state of the MCS microprocessor's lower address bus AD7-0 during memory accesses. The AD7-0 bus 4 also serves as the data bus between the MCS microprocessor 1 and the external memory 12 on a time-multiplexed basis. The address bus 3 delivers MCS microprocessor address A15-8 to the external memory 12. Three extra pins, P1.0, P1.1 and P1.2 of the MCS microprocessor 1 are connected to address pins A18, A17 and A16 respectively. Therefore the MCS microprocessor can access a one-eighth portion of the external memory 12 by setting the proper state of the P1.0, P1.1 and P1.2 pins.
By dividing the external memory 12 into eight 64K-byte portions, or pages, which are switchable by pins P1.0, P1.1 and P1.2, the MCS microprocessor 1 is granted full access to the 512K-byte external memory 12. FIG. 2 shows the organization of the external memory 12 as is visible to the MCS microprocessor 1. While the capacity of each page is 64K bytes, a common area in each page with certain capacity (e.g. 10K bytes) must be reserved for storing the interrupt vector table, interrupt service routines, general functions and other data. Because the common area data is duplicated at the same relative location in each page, the MCS microprocessor 1 is able to access the common data regardless of the state of pins P1.0-2. For example, assuming that the processor has to execute a program in page 2 in response to an interrupt while executing a program in page 1, it may first execute a memory page switching routine residing in the common area. The routine sets the P1.0-2 pin state for page 2, then transfers the program flow to the target program in page 2. After executing the program in the page 2, the processor may return to page switching program in the common area, change the page select pin state back to page 1, and then the processor can return to the address of the program in page 1 to continue executing the program.
According to the foregoing description, though the largest capacity of the external memory of the MCS-51/52 series microprocessor is 64K bytes, the external memory can be further expanded by switching the plurality of memory banks when using the extra pins of the microprocessor as the decode lines to set the address of the external memory with capacity of over 64K bytes. However, each memory bank has to reserve a certain space for the common area storing common data. As a result, multiples sets of common area are allocated in the external memory, as shown in FIG. 3, so the space of the external memory can not be utilized efficiently.